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BCS

Current Report · Items 7.01, 9.01 · 8-K

D-Wave Quantum Inc.

Regulation FD Disclosure

Item 7.01 Regulation FD Disclosure. On August 5, 2026, D-Wave Quantum Inc. (“D-Wave”) announced a major research breakthrough advancing the path to practical, fault-tolerant gate-model quantum computing.…

Filed Aug 5, 2026Accepted Aug 5, 2026, 11:09 AM EDTCIK 1907982Accession 0001907982-26-000123
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Company context

Current securities

Historical securities (2)

Recent company filings

  1. 4 filingOct 30, 2026
  2. 3 filingOct 30, 2026
  3. Regulation FD DisclosureOct 28, 2026
  4. 4 filingOct 16, 2026
  5. Regulation FD DisclosureOct 1, 2026

Registered securities in this filing

D-Wave Quantum Inc. · 8-K · Filed 2026-08-05

As filed in this accession. Current/historical status below comes from the governed listing record; the cover itself remains exact to this filing.

Common stock, par value $0.0001 per share

Symbol
QBTS
Exchange
NASDAQ
Classification
COMMON
Filing context

Context: c-1

Dimensions: Not supplied

Accession 000190798226000123 · 1 registered-security cover member

Read the exact SEC filing ↗

Disclosure sections

Items 7.01, 9.01

Select an item to read the extracted section. The as-filed document remains the primary evidence.

Item 7.01Item 7.01 - Regulation FD Disclosure
Item 7.01 Regulation FD Disclosure. On August 5, 2026, D-Wave Quantum Inc. (“D-Wave”) announced a major research breakthrough advancing the path to practical, fault-tolerant gate-model quantum computing. Published in the peer-reviewed scientific journal Nature, the research demonstrates a fast, high-fidelity, two-qubit entangling gate that preserves the error-correction advantages of D-Wave’s superconducting dual-rail qubit architecture. The results address one of the industry’s most consequential challenges by reducing the immense quantum and classical hardware overhead typically required to detect and correct quantum errors as systems scale. The paper, “An entangling gate for dual-rail erasure qubits,” details a new two-qubit entangling gate, a fundamental building block of quantum computation, designed to support efficient quantum error correction. The research demonstrates approximately 99.9% fidelity during two-qubit operations, with fast gate times of about 500 nanoseconds, enabled by native hardware-level error detection. Leveraging these results, D-Wave simulations indicate its dual-rail architecture could reduce the logical error rate by as much as a factor of 10 for each increment in error correction, significantly reducing the physical qubit overhead required for fault-tolerant quantum computing. According to D-Wave’s CEO, Dr. Alan Baratz, this research demonstrates that D-Wave’s dual-rail architecture combines fast superconducting operations with high-fidelity performance while preserving native hardware-level error detection. D-Wave believes this work confirms that its path to commercial fault-tolerant quantum computing is practical and achievable. A copy of the press release is attached as Exhibit 99.1. The information in this Item 7.01 to this Current Report on Form 8-K, including Exhibit 99.1, is intended to be furnished and shall not be deemed to be “filed” for purposes of Section 18 of the Securities Exchange Act of 1934, as amended (the “Exchange Act”), or otherwise subject to the liabilities of that section, nor shall such information be deemed incorporated by reference in any filing under the Securities Act of 1933, as amended, or the Exchange Act, except as expressly set forth by specific reference in such a filing.

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